How to Test PCIe® 5.0 Receiver Compliance
Setting up a receiver compliance test for a PCIe® 5.0 device
To ensure interoperability, PCIe 5.0 devices need to pass receiver compliance tests for certification by the PCI-Special Interest Group (PCI-SIG®). PCIe 5.0 technology encompasses both the base specification for silicon-level development and the card electromechanical (CEM) specification for motherboards and add-in cards. The physical layer (PHY) test specification provides guidance for testing using the CEM form factor.
Before conducting a receiver test, a bit error ratio tester (BERT) pattern generator must be calibrated with an oscilloscope to transmit a worst-case stress test signal. This process involves adding impairments, including incremental loss-induced intersymbol interference (ISI). After calibration, the receiver of the device under test (DUT) applies the test signal, measuring parameters such as the bit error ratio.
PCIe 5.0 receiver compliance test solution
Explore products in our PCIe 5.0 receiver compliance test solution
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![D9020ASIA Advanced Signal Integrity Software (Crosstalk)]()
D9020ASIA Advanced Signal Integrity Software (Crosstalk)
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![M8040A 64 GBaud High-Performance BERT]()
M8040A 64 GBaud High-Performance BERT
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![UXR0504B Infiniium UXR-Series Oscilloscope: 50 GHz, 4 Channels]()
UXR0504B Infiniium UXR-Series Oscilloscope: 50 GHz, 4 Channels
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![N5991PC5A PCI Express 5 CEM Receiver Test Automation]()
N5991PC5A PCI Express 5 CEM Receiver Test Automation
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