How to Test PCIe® 5.0 Receiver Compliance
Setting up a receiver compliance test for a PCIe® 5.0 device
To ensure interoperability, PCIe 5.0 devices need to pass receiver compliance tests for certification by the PCI-Special Interest Group (PCI-SIG®). PCIe 5.0 technology encompasses both the base specification for silicon-level development and the card electromechanical (CEM) specification for motherboards and add-in cards. The physical layer (PHY) test specification provides guidance for testing using the CEM form factor.
Before conducting a receiver test, a bit error ratio tester (BERT) pattern generator must be calibrated with an oscilloscope to transmit a worst-case stress test signal. This process involves adding impairments, including incremental loss-induced intersymbol interference (ISI). After calibration, the receiver of the device under test (DUT) applies the test signal, measuring parameters such as the bit error ratio.
PCIe 5.0 receiver compliance test solution
Explore products in our PCIe 5.0 receiver compliance test solution
-
![D9020ASIA Advanced Signal Integrity Software (Crosstalk)]()
D9020ASIA Advanced Signal Integrity Software (Crosstalk)
-
![M8040A 64 GBaud High-Performance BERT]()
M8040A 64 GBaud High-Performance BERT
-
![N5991PC5A PCI Express 5 CEM Receiver Test Automation]()
N5991PC5A PCI Express 5 CEM Receiver Test Automation
-
![UXR0504B Infiniium UXR-Series Oscilloscope: 50 GHz, 4 Channels]()
UXR0504B Infiniium UXR-Series Oscilloscope: 50 GHz, 4 Channels
Discover resources and insights
Additional resources for PCIe 5.0 receiver compliance testing
Related use cases
-
![How to Test USB4 Version 2.0 Receiver Compliance]()
How to Test USB4 Version 2.0 Receiver Compliance
USB4 Version 2.0 receiver testing requires precise stress signal calibration, consistently repeatable pattern generation, and bit error rate measurements. Learn how to perform a USB4 Version 2.0 receiver compliance test using a bit error ratio tester (BERT), a high-bandwidth oscilloscope, USB receiver test application software, and the USB-IF SigTest utility.
Learn more
-
![How to Test USB4 Receiver Compliance]()
How to Test USB4 Receiver Compliance
Testing physical layer (PHY) USB4 electrical performance requires executing conformance tests defined by the Universal Serial Bus Implementers Forum (USB-IF). Learn how to tune and calibrate a bit error ratio tester's (BERT) stress signal amplitude, channel equalization, and insertion loss to achieve accurate stress conditions required for conformance testing.
Learn more
-
![How to Test and Debug DDR4 Systems]()
How to Test and Debug DDR4 Systems
Engineers implementing DDR4 systems and memory require a solution that provides trace capture and analysis, enabling insights needed to understand system behavior. Learn how to test your DDR4 memory system’s performance and protocol functionality analysis for complete compliance.
Learn more
Get in touch with one of our experts
Need help finding the right solution for you?
PCI-SIG®, PCIe®, and the PCI Express® are US registered trademarks and/or service marks of PCI-SIG.