W6600A Series LPDDR4 BGA Interposers

W6600A Series LPDDR4 BGA Interposers

Data Sheets

Keysight W6600A Series

LPDDR4 BGA Interposers

Data Sheet

Introduction

The Keysight Technologies, Inc. W6600A Series LPDDR4 BGA interposers enable probing of embedded memory LPDDR4 DRAM from the ball grid array with Keysight U4164A logic analyzers.

The W6600A Series LPDDR4 BGA interposers are designed to take full advantage of quad sample state mode on U4164A modules with Option 02G, requiring only a single probe point for up to four samples at two different thresholds. W6600A Series BGA interposers are tested up to 3200 MT/s data rates.

W6601A: LPDDR4 200 BGA Interposer 2-Wing, 3.2 Gb/s, CA Channel A, Partial DQ

LPDDR4 200-ball DRAM are dual x16 channel devices. They can be used as two single x16 channel devices or as a single x32 device.

The W6601A LPDDR4 200-ball BGA interposer is designed to satisfy functional debug and validation for LPDDR4 200-ball chip down systems using the DRAM as a single, 32-bit channel. If the DRAM is used as two channels, then the W6601A will only provide visibility to the logic analyzer for the CA and commands for Bank 0 and Bank 1 from Channel A.

W6601A wings are designed to connect using one U4208A and one U4209A 61 pin ZIF probe/cables into a single U4164A logic analyzer.

Routing and cabling for the signals is single touch probing and is compatible with both Quad Sample State mode and Quarter Channel Timing modes of the U4164A logic analyzer. The exception is that Reset and CKE1 are NOT visible in Quarter Channel Timing mode, as those signals route into pods (3 and 7) and those pods loose the CK inputs when in Quarter Channel Timing mode. Quad Sample State mode is available only with Option -02G of the U4164A. Quarter Channel Timing mode is available in both Options -01G and -02G.

Software configurations for Quad Sample Timing mode and Quarter Channel Timing mode will be different as the labeling for Read /Write separation and rising /falling edges are not required in Timing modes.

At speeds under 2500 Mb/s, the W6601A can be used with dual-clock edge clocking and Dual-Sample mode instead of Quad Sample mode. Even in this reduced speed mode, it is recommended that the W6601A be used with a U4164A as the U4164A is the only LA with dual thresholds for Read/Write separation in Dual Sample mode.

Not all DQ are visible to the LA. This is due to routing limitations (even using single touch probing and the denser 61 pin ZIF). Refer to the W6601A pinout for the signals probed.

The U4208A connects to the left side of the W6601A and the U4209A connects to the right wing.

W6602A: RC BGA Interposer, LPDDR4 200-Ball, Rigid, 3.2 Gb/s, CHA and CHB All DQ

The Keysight W6602A+U4207A passively monitors the LPDDR4 200 ball DRAM package. After tuning the Keysight analyzer, Command/Address bits can be reliably captured up to 3200 MT/s. At some data rates, the analyzer may not be able to provide an error-free capture of all DQ data bits.

LPDDR4 200-ball DRAM are dual x16 channel devices. They can be used as two single x16 channel devices or as a single x32 device. The W6602A LPDDR4 200-ball BGA interposer is designed to satisfy functional debug and validation for LPDDR4 200-ball chip down systems using the DRAM as either two single 16 bit channels or a single, 32-bit channel.

Software configurations

The W6602A interposer can be used in the following seven logic analyzer software configurations; probing connections to the U4164A modules are unique for different configurations:

  • 10 GHz timing mode
  • CHA state mode 16 DQ under 2500MT/s (double edge clocking)
  • CHA state mode 16 DQ over 2500MT/s (single edge clocking)
  • CHA state mode 32 DQ under 2500MT/s (double edge clocking)
  • CHA state mode 32 DQ over 2500MT/s (single edge clocking)
  • CHB state mode 16 DQ under 2500MT/s (double edge clocking)
  • CHB state mode 16 DQ over 2500MT/s (single edge clocking)

This interposer effectively utilizes the single touch probing and quad sampling features of the U4164A logic analyzer module, thereby allowing you to probe LPDDR4 DQ signals above 2.5 Gb/s without double probe load. (In quad sampling, four samples are captured per clock edge at two different thresholds. Two samples are taken at each threshold.) The Quad Sample State mode is only available with the U4164A-02G licensed speed grade option.

Software

Default configurations for the W6600A Series interposers are included in the standard B4661A memory analysis software package. The Keysight B4661A memory analysis software provides four standard software features and four licensed memory analysis options.

B4661A standard software features

  • Default configurations for DDR and LPDDR probing solutions for Keysight logic analyzers. There are three default SW configurations for the W6601A:
  • 10 GHz Timing mode
  • State mode under 2500 Mb/s (double edge clocking)
  • State mode over 2500 Mb/s (single edge clocking)
  • DDR setup assistant
  • DDR eye finder/eye scan
  • DDR configuration creator

The Keysight B4661A memory analysis software offers a suite of viewers and tools that include the industry’s first protocol compliance violation testing capability across speed changes, a condensed traffic overview for rapid navigation to areas of interest in the logic analyzer trace, powerful performance analysis graphics, and DDR and LPDDR decoders. With the B4661A memory analysis software and a Keysight logic analyzer 1, users can monitor DDR3/4 or LPDDR2/3/4 systems to debug, improve performance, and validate protocol compliance. Powerful traffic overviews, multiple viewing choices, and real-time compliance violation triggering help identify elusive DDR/LPDDR system violations.